V200 is designed as a Combinational Board Tester with Digital / Analog and Mixed Signal Test capabilities through simple clips and probes or through card edge or as a cluster tester with a special test fixture for up to 96 (Digital) 256 (Analog) test pins. In addition, it has the fully integrated Boundary Scan Test option for virtual pin test concept, where the number of virtual test pins has no physical limit. It’s has user programmable test speed and can generate test patterns at 10MHz data rate.
V200 can perform In-Circuit Functional Test, testing individual lCs in In-Circuit or Out-of-Circuit with Pin Status Check & has In-built DRC (Design Rule Checker). V200 Utilizes IEEE Standard VHDL language based device library for digital devices. For Analog / Mixed Signal Devices, Python TD Test languages based scripts are available for stimulus and output evaluation.
Auto compensation and Identify unknown or house coded devices are extended for all digital devices (not limiting to SSI/MSI) and thus LSI / VLSI chips can be tested / identified in its In-Circuit configuration without the need to learn / remove from a known good board.
V200’s QSMVI Stimulus for VI Trace can be used from available Standard or from user defined wave pattern, thus not limiting the VI trace to simple sine wave alone. User defined wave pattern can be any mathematical wave Shape such as sine / triangle / square / ramp or even arbitrary patterns as desired by user and can be stored in the Library for possible re-use. The frequency is fully programmable from as fast as 100 KHz as a result of V200's vast time base selection capability.
"Best Fit Curve" - a unique feature, where the best drive pattern is automatically suggested to the user for the characteristics of the UUT to increase the fault coverage with advanced algorithm suggests the failing pin within A device with% probability.
V200 can perform Resistance, Inductance, Capacitance, Voltage and Frequency Measurement along with 3 Channel - 10Mega Sample Scope with Programmable Load and 3 Channel Function Generator.
V200 with TD6 Test Sequencer software allows Sequencing of multiple test using combination of isolated device test (ICFT), QSMVI, Measurements, Card Edge Functional Test, Integrated Card Edge +Boundary Scantest ', all in one test program.
Test Sequencer Software allows graphical TPS development using JPEG image of the PCB under test, tagging devices and pins. Adding tests to the devices, cluster is with just a right click of the mouse. Learn, verify and test options using mouse click on the device location.
Using V200 Card Edge Functional Test for complex boards with ASICs and BGAs, where no functional data are available, user can generate the test vectors using the graphical waveform editor or Python TD test vector generator, where the primary IO pins can be either physical edge pin or In Circuit pin or a JTAG Virtual Boundary Scan Pin. User can either learn the expected output from a known good board or define the expected output using graphical waveform editor or simulate the expected output using VHDL Simulation or the Python TD test language with mask or tolerance editing facilities. Test program developed can be used for a device or cluster or a complete PCB.
CircuitTracer (Optional) This optional software package helps the user to trace the intra links between the pins of an IC and also the interlinks between pins of various ICs which can be accessed through appropriate test clips. It automatically generates the Netlists. The Netlist file is then converted to file formats, which are compatible to CAD software packages like ORCAD or EDWIN. This process helps in Reverse Engineering of the PCB i.e. to generate the Schematic Diagram / Circuit Diagram of the Board Under Test.
IDDE is an Optional Software Package which is extremely useful for Device Test Program Generation. IDDE stands for Integrated Device Development Environment using VHDL and PythonTD test languages. Complete with automatic fault simulation nad fault coverage report for every library digital device developed. Also included is GTPG whereuser can directly define the required test input waveforms for the Device Under Test or the entire Board Under Test graphically and if the expected Output waveforms are known to the user the same also can be defined. Otherwise the output from Known Good Board can be learnt and stored as master reference for future comparisons. This mode is extremely useful to test devices / simple boards without any need to write complex test programs.Russian Libray
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Boundary Scan Software: Includes Chain detection, Chain integrity test, Device ID, User ID, Interconnect test in Interacive and additionally Interconnect test between JTAG pins and Physical test pin / edge connector, Functional test for non boundary scan devices in berween JTAG devices and between JTAG and edge connector devices including Guided probe back tracking in advanved Boundary Scan test software.
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